DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

—Intel® Quark SoC X1000

27 Intel® Quark SoC X1000 Absolute Maximum Voltage Ratings ......................................... 69

28 Power Supply Rail Ranges ......................................................................................... 70

29 Maximum Supply Current: ICC Max ............................................................................ 71

30 CFIO AC Characteristics ............................................................................................ 72

31 RTC DC Characteristics ............................................................................................. 72

32 PCI Express* 2.0 Differential Signal DC Characteristics ................................................. 73

33 PCI Express* 2.0 Interface Timings ............................................................................ 73

34 USB 2.0 Differential Signal DC Characteristics .............................................................. 75

35 USB 2.0 Interface Timings......................................................................................... 76

36 Legacy SPI Interface Timings (20 MHz) ....................................................................... 78

37 SPI0/1 Interface Timings (25 MHz)............................................................................. 78

38 SDIO Timing ........................................................................................................... 79

39 Reference Clocks AC Characteristics ........................................................................... 80

40 Fixed I/O Register Access Method Example (NSC Register) ............................................ 83

41 Fixed Memory Mapped Register Access Method Example (IDX Register)........................... 83

42 Referenced I/O Register Access Method Example (PM1S Register) .................................. 84

43 Memory Mapped Register Access Method Example (ESD Register) .................................. 84

44 PCI Register Access Method Example (PCI_DEVICE_VENDOR Register)............................ 84

45 PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping ............................................ 85

46 PCI Configuration Memory Bar Mapping ...................................................................... 85

47 MCR Description ...................................................................................................... 86

48 MCRX Description..................................................................................................... 86

49 Register Access Types and Definitions......................................................................... 87

50 Fixed Memory Ranges in the Legacy Bridge ................................................................. 93

51 Fixed I/O Ranges in the Legacy Bridge ........................................................................ 94

52 Movable I/O Ranges Decoded by PCI Devices on the I/O Fabric ...................................... 94

53 PCI Devices and Functions......................................................................................... 95

54 Intel® Quark SoC X1000 Clock Inputs....................................................................... 101

55 Intel® Quark SoC X1000 Clock Outputs..................................................................... 101

56 General Power States for System ............................................................................. 104

57 ACPI PM State Transition Rules ................................................................................ 104

58 Processor Core/ States Support................................................................................ 105

59 Main Memory States ............................................................................................... 105

60 PCIe* States ......................................................................................................... 105

61 G, S and C State Combinations ................................................................................ 106

62 RTC Power Well Timing Parameters .......................................................................... 111

63 S4/S5 to S0 Timing Parameters ............................................................................... 115

64 Intel® Quark SoC X1000 S3 Wake Events ................................................................. 116

65 SoC Reset Events................................................................................................... 117

66 Summary of PCI Configuration Registers—0/0/0......................................................... 129

67 Summary of I/O Registers—PMBA ............................................................................ 134

68 Summary of I/O Registers—SPI_DMA_BAR ................................................................ 136

69 Summary of Message Bus Registers—0x00 ................................................................ 138

70 Summary of Message Bus Registers—0x03 ................................................................ 142

71 Summary of Message Bus Registers—0x04 ................................................................ 171

72 Summary of Message Bus Registers—0x05 ................................................................ 180

73 Summary of Message Bus Registers—0x05 ................................................................ 228

74 Summary of Message Bus Registers—0x31 ................................................................ 229

75 Memory Signals ..................................................................................................... 233

76 Supported DDR3 DRAM Devices ............................................................................... 235

77 Supported DDR3 Memory Configurations ................................................................... 235

78 Summary of Message Bus Registers—0x01 ................................................................ 236

79 PCI Express* 2.0 Signals......................................................................................... 259

80 Possible Interrupts Generated From Events/Packets.................................................... 260

81 Summary of PCI Configuration Registers—0/23/0 ....................................................... 262

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

33

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