DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Electrical Characteristics—Intel® Quark SoC X1000
Table 37.
SPI0/1 Interface Timings (25 MHz)
Sym
Parameter
Min
Max
Units Notes
Fig
TSSCF
Setup of SPI0/1_SS_B with respect to first
edge out of inactive state of SPI0/1_SCK
20
—
ns
9
TCLSH
Hold of SPI0/1_SS_B with respect to last
edge into inactive state of SPI0/1_SCK
20
—
ns
9
Note:
1.
2.
3.
4.
All input signals have a slope of 1.0ns measured between 20%and 80% VCC values
All output signals are loaded with 20pF
Measurements are made at
Driving edge and capturing
50%
edge
oVfCCSPleI0ve/1ls_SCK
are
determined
by
SPI
Control
Register
1
settings
SSCR1.SPH and SSCR1.SPO; Figure 9 shows SPI_SCK rising edge as the driving edge and SPI_SCK
falling edge as the capturing edge by way of example
Figure 9. SPI Interface Timing
TCH
TCL
SPI_SCK
SPI_MOSI
TCDDV
TSSCF
SPI_SS_B
SPI_MISO
TDSCC TCCDH
TCLSH
4.8.3
SDIO Interface Timing
Table 38. SDIO Timing (Sheet 1 of 2)
Sym
F
TCH
TCL
TDSCR
Parameter
Operating Frequency SD_CLK
Clock High Time SD_CLK
Clock Low Time SD_CLK
SD_DATA[7:0]/SD_CMD setup time
with respect to SD_CLK rising
Min
-
10
10
0.6
Max
50
-
-
-
Units Notes Fig
MHz
ns
10
ns
10
ns
10
October 2013
Document Number: 329676001US
Intel® Quark SoC X1000
DS
79
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