Intel® Quark SoC X1000—Electrical Characteristics
Table 38.
SDIO Timing (Sheet 2 of 2)
Sym
Parameter
Min
Max
Units Notes Fig
TCRDH
SD_DATA[7:0]/SD_CMD hold time
with respect to SD_CLK rising
1.6
-
10
TCFDV
SD_CLK falling to data valid on
SD_DATA[7:0]/SD_CMD
-2.0
2.7
ns
10
Note:
1.
2.
3.
All input signals have a slope of 1.0ns measured between 20%and 80% VCC values
All output signals are loaded with 20pF
Measurements are made at 50% VCC levels
Figure 10. SDIO Interface Timing
TCL
TCH
SD_CLK
TCFDV
SD_DATA[7:0]
SD_CMD
(outputs)
SD_DATA[7:0]
SD_CMD
(inputs)
TDSCR TCRDH
4.9
4.9.1
Clock AC Timing
Reference Clock AC Characteristics
Table 39. Reference Clocks AC Characteristics (Sheet 1 of 2)
Parameter
Description
Min
Max
Units
Notes
Fig
Associated Signals:
REF0_OUTCLK_P, REF0_OUTCLK_N,
REF1_OUTCLK_P, REF1_OUTCLK_N
Related Supply:
VCCAICLKDBUFF_1P0
TSLEW_RISE
TSLEW_FALL
PSLEW_VAR
VSWING
VCROSS
VCROSS_DELTA
Rising slew rate
Falling slew rate
Slew rate matching
Differential output swing
Crossing point voltage
VCROSS variation
1.5
8.0
V/ns
2,3,10
11
1.5
8.0
V/ns
2,3,10
11
-
20
%
1,9,10
11
300
-
mV
2,11
11
300
550
mV
1,4,5,11
11
-
140
mV
1,4,8,11
11
Intel® Quark SoC X1000
DS
80
October 2013
Document Number: 329676001US