ST7LITEU05 ST7LITEU09
11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT)
11.1.1 Introduction
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 13-
bit upcounter with two software-selectable time-
base periods, an 8-bit input capture register and
watchdog function.
11.1.2 Main Features
■ Realtime Clock
– 13-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz fOSC)
– Maskable timebase interrupt
■ Input Capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
Figure 34. Lite Timer Block Diagram
■ Watchdog
– Enabled by hardware or software (configura-
ble by option byte)
– Optional reset on HALT instruction (configura-
ble by option byte)
– Automatically resets the device unless disable
bit is refreshed
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
fLTIMER
To 12-bit AT TImer
fOSC
13-bit UPCOUNTER
fWDG
/2
fLTIMER
1
Timebase
0
1 or 2 ms
(@ 8MHz
fOSC)
WATCHDOG
WATCHDOG RESET
LTICR
8 MSB
LTIC
8-bit
INPUT CAPTURE
REGISTER
LTCSR
ICIE ICF
7
TB TBIE
TBF
WDG
RF
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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