ST7PLITEU09M3TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLITEU09M3TR

8-bit MCU with single voltage Flash memory, ADC, timers

STMicroelectronics 

ST7LITEU05 ST7LITEU09

12-BIT AUTORELOAD TIMER (Cont’d)

Figure 39. PWM Signal Example

fCOUNTER

COUNTER

FFDh

ATR= FFDh

FFEh

FFFh

FFDh

FFEh

FFFh

FFDh

FFEh

DCR0=FFEh

Output Compare Mode

To use this function, the OE bit must be 0, other-

wise the compare is done with the shadow register

instead of the DCRx register. Software must then

write a 12-bit value in the DCR0H and DCR0L reg-

isters. This value will be loaded immediately (with-

out waiting for an OVF event).

The DCR0H must be written first, the output com-

pare function starts only when the DCR0L value is

written.

When the 12-bit upcounter (CNTR) reaches the

value stored in the DCR0H and DCR0L registers,

the CMPF0 bit in the PWM0CSR register is set

and an interrupt request is generated if the CMPIE

bit is set.

Note: The output compare function is only availa-

ble for DCRx values other than 0 (reset value).

Caution: At each OVF event, the DCRx value is

written in a shadow register, even if the DCR0L

value has not yet been written (in this case, the

shadow register will contain the new DCR0H value

and the old DCR0L value), then:

– If OE=1 (PWM mode): the compare is done be-

tween the timer counter and the shadow register

(and not DCRx)

– if OE=0 (OCMP mode): the compare is done be-

tween the timer counter and DCRx. There is no

PWM signal.

t

The compare between DCRx or the shadow regis-

ter and the timer counter is locked until DCR0L is

written.

11.2.4 Low Power Modes

Mode

Description

SLOW

The input frequency is divided

by 32

WAIT

No effect on AT timer

ACTIVE-HALT

AT timer halted except if CK0=1,

CK1=0 and OVFIE=1

HALT

AT timer halted

11.2.5 Interrupts

Interrupt

Event 1)

Event

Flag

Enable Exit Exit

Control from from

Bit Wait Halt

Overflow

Event

OVF OVFIE Yes No

CMP Event CMPFx CMPIE Yes No

Exit

from

Active-

Halt

Yes2)

No

Note 1: The interrupt events are connected to sep-

arate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in

the ATCSR register and the interrupt mask in the

CC register is reset (RIM instruction).

Note 2: only if CK0=1and CK1=0

60/115

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