ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
12 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
12.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the MISCR1 miscellaneous regis-
ter. This control allows to have two fully independ-
ent external interrupt source sensitivities.
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
12.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■ Main clock signal (fCPU) output on PF0
■ A beep signal output on PF1 (with 3 selectable
audio frequencies)
■ SPI pin configuration:
– SS pin internal control to use the PC7 I/O port
function while the SPI is active.
These functions are described in detail in the Sec-
tion 12 "MISCELLANEOUS REGISTERS" on
page 47.
Figure 27. Ext. Interrupt Sensitivity
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PF0
PF1
PF2
MISCR1
INTERRUPT
SOURCE
ei2
ei3
IS10 IS11
SENSITIVITY
CONTROL
MISCR1
INTERRUPT
SOURCE
ei0
ei1
IS20 IS21
SENSITIVITY
CONTROL
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