ST72334J4TC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72334J4TC
STMicroelectronics
ST72334J4TC Datasheet PDF : 150 Pages
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
MISCELLANEOUS REGISTERS (Cont’d)
12.3 REGISTERS DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
ei0 (port A3..0) and ei1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
ei2 (port B3..0) and ei3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
External Interrupt Sensitivity
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
IS11 IS10
00
01
10
11
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(fOSC/2 on I/O port)
Note: To reduce power consumption, the MCO
function is not active in Active Halt mode.
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These 2
bits are set and cleared by software.
fOSC / 4
fOSC / 8
fOSC / 16
fOSC / 32
fCPU in Slow mode
CP1 CP0
00
10
01
11
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.
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