DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

7.3 Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The dsPIC33EVXXXGM00X/10X family devices clear

their registers in response to a Reset, which forces the

PC to zero. The device then begins program execution

at location, 0x000000. A GOTO instruction at the Reset

address can redirect program execution to the

appropriate start-up routine.

Note:

Any unimplemented or unused vector

locations in the IVT should be pro-

grammed with the address of a default

interrupt handler routine that contains a

RESET instruction.

7.4 Interrupt Control and Status

Registers

dsPIC33EVXXXGM00X/10X family devices implement

the following registers for the interrupt controller:

• INTCON1

• INTCON2

• INTCON3

• INTCON4

• IFSx

• IECx

• IPCx

• INTTREG

7.4.1 INTCON1 THROUGH INTCON4

Global interrupt control functions are controlled from

the INTCON1, INTCON2, INTCON3 and INTCON4

registers.

INTCON1 contains the Interrupt Nesting Disable bit

(NSTDIS), as well as the control and status flags for the

processor trap sources.

The INTCON2 register controls external interrupt

request signal behavior and also contains the Global

Interrupt Enable bit (GIE).

INTCON3 contains the status flags for the DMT (Dead-

man Timer), DMA and DO stack overflow status trap

sources.

The INTCON4 register contains the ECC Double-Bit

Error (ECCDBE) and Software-Generated Hard Trap

(SGHT) status bit.

7.4.2 IFSx

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is

set by the respective peripherals or external signal and

is cleared through software.

7.4.3 IECx

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

7.4.4 IPCx

The IPCx registers are used to set the Interrupt Priority

Level (IPL) for each source of interrupt. Each user

interrupt source can be assigned to one of eight priority

levels.

7.4.5 INTTREG

The INTTREG register contains the associated

interrupt vector number and the new CPU Interrupt

Priority Level, which are latched into Vector Number

(VECNUM<7:0>) and Interrupt Priority Level bit

(ILR<3:0>) fields in the INTTREG register. The new

Interrupt Priority Level is the priority of the pending

interrupt.

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence as they are

listed in Table 7-1. For example, the INT0 (External

Interrupt 0) is shown as having Vector Number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP

bits in the first position of IPC0 (IPC0<2:0>).

7.4.6 STATUS/CONTROL REGISTERS

Although these registers are not specifically part of the

interrupt control hardware, two of the CPU Control

registers contain bits that control interrupt functionality.

For more information on these registers, refer to

“CPU” (DS70359) in the “dsPIC33/PIC24 Family

Reference Manual”.

• The CPU STATUS Register, SR, contains the

IPL<2:0> bits (SR<7:5>). These bits indicate the

current CPU Interrupt Priority Level. The user

software can change the current CPU Interrupt

Priority Level by writing to the IPLx bits.

• The CORCON register contains the IPL3 bit

which, together with IPL<2:0>, also indicates the

current CPU Interrupt Priority Level. IPL3 is a

read-only bit so that trap events cannot be

masked by the user software.

All Interrupt registers are described in Register 7-3 to

Register 7-7.

DS70005144E-page 100

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