DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

7.0 INTERRUPT CONTROLLER

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this

data sheet, refer to “Interrupts”

(DS70000600) in the “dsPIC33/PIC24

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The dsPIC33EVXXXGM00X/10X family interrupt con-

troller reduces the numerous peripheral interrupt

request signals to a single interrupt request signal to

the dsPIC33EVXXXGM00X/10X CPU. The Interrupt

Vector Table (IVT) provides 246 interrupt sources

(unused sources are reserved for future use) that can

be programmed with different priority levels.

The interrupt controller has the following features:

• Interrupt Vector Table with up to 246 Vectors

• Alternate Interrupt Vector Table (AIVT)

• Up to Eight Processor Exceptions and Software

Traps

• Seven User-Selectable Priority Levels

• Interrupt Vector Table (IVT) with a Unique Vector

for Each Interrupt or Exception Source

• Fixed Priority within a Specified User Priority Level

• Fixed Interrupt Entry and Return Latencies

• Software can Generate any Peripheral Interrupt

• Alternate Interrupt Vector Table (AIVT) is

available if Boot Security is Enabled and

AIVTEN = 1

7.1 Interrupt Vector Table

The dsPIC33EVXXXGM00X/10X family IVT, shown

in Figure 7-2, resides in program memory, starting at

location, 000004h. The IVT contains seven non-

maskable trap vectors and up to 187 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with Vector 0 takes priority over interrupts at any other

vector address.

7.2 Alternate Interrupt Vector Table

The Alternate Interrupt Vector Table (AIVT), shown in

Figure 7-1, is available if the Boot Segment (BS) is

defined, the AIVTEN bit is set in the INTCON2 register

and if the AIVTDIS Configuration bit is set to ‘1’. The

AIVT begins at the start of the last page of the Boot

Segment.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 95

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