DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

6.0 RESETS

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X family

of devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to “Reset” (DS70602) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

• MCLR: Master Clear Pin Reset

• SWR: RESET Instruction

• WDTO: Watchdog Timer Time-out Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

- Illegal Address Mode Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST

signal active. On system Reset, some of the registers

associated with the CPU and peripherals are forced to

a known Reset state and some are unaffected.

Note:

Refer to the specific peripheral section or

Section 4.0 “Memory Organization” of

this device data sheet for register Reset

states.

All types of device Reset set a corresponding status bit

in the RCON register to indicate the type of Reset (see

Register 6-1).

A POR clears all the bits, except for the POR and BOR

bits (RCON<1:0>) that are set. The user application

can set or clear any bit at any time during code

execution. The RCON bits only serve as status bits.

Setting a particular Reset status bit in software does

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in the other

sections of this device data sheet.

Note:

The status bits in the RCON register

should be cleared after they are read.

Therefore, the next RCON register value

after a device Reset is meaningful.

Note:

In all types of Resets, to select the device

clock source, the contents of OSCCON are

initialized from the FNOSCx Configuration

bits in the FOSCSEL Configuration register.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 91

Share Link: