DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology
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DSPIC33EV64GM102-I/SO
Microchip Technology
DSPIC33EV64GM102-I/SO Datasheet PDF : 500 Pages
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dsPIC33EVXXXGM00X/10X FAMILY
4.3.4 SOFTWARE STACK
The W15 register serves as a dedicated Software
Stack Pointer (SSP) and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This simpli-
fies reading, writing and manipulating the SSP (for
example, creating stack frames).
Note:
To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EVXXXGM00X/10X family devices and per-
mits stack availability for non-maskable trap exceptions.
These can occur before the SSP is initialized by the
user software. You can reprogram the SSP during
initialization to any location within the Data Space.
The SSP always points to the first available free word
and fills the software stack, working from lower toward
higher addresses. Figure 4-14 illustrates how it pre-
decrements for a stack pop (read) and post-increments
for a stack push (writes).
When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
PC<22:16> are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in Figure 4-14. During exception processing,
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS Register (SR). This allows the
contents of SRL to be preserved automatically during
interrupt processing.
Note 1: To maintain system SSP (W15) coher-
ency, W15 is never subject to (EDS) pag-
ing, and is therefore, restricted to an
address range of 0x0000 to 0xFFFF. The
same applies to the W14 when used as a
Stack Frame Pointer (SFA = 1).
2: As the stack can be placed in, and can
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a
‘C’ development environment.
FIGURE 4-14:
0x0000 15
CALL STACK FRAME
0
CALL SUBR
PC<15:0>
b‘000000000’ PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
4.4 Instruction Addressing Modes
The addressing modes shown in Table 4-45 form the
basis of the addressing modes optimized to support the
specific features of the individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction types.
4.4.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a Working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire Data Space.
4.4.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where, Operand 1 is always a Working register (that
is, the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a
W register fetched from data memory or a 5-bit literal.
The result location can be either a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
Note:
Not all instructions support all of the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
DS70005144E-page 74
2013-2016 Microchip Technology Inc.
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