DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-45: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode

Description

File Register Direct

The address of the file register is specified explicitly.

Register Direct

The contents of a register are accessed directly.

Register Indirect

The contents of Wn form the Effective Address (EA).

Register Indirect Post-Modified

The contents of Wn form the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-Modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

(Register Indexed)

Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

4.4.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP accumulator class of

instructions provide a greater addressing flexibility than

other instructions. In addition to the addressing modes

supported by most MCU instructions, move and accu-

mulator instructions also support Register Indirect with

Register Offset Addressing mode, also referred to as

Register Indexed mode.

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared by both source and destination

(but typically only used by one).

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-Bit Literal

• 16-Bit Literal

Note:

Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

4.4.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred

to as MAC instructions, use a simplified set of addressing

modes to allow the user application to effectively

manipulate the Data Pointers through register indirect

tables.

The Two-Source Operand Prefetch registers must be

members of the set, {W8, W9, W10, W11}. For data

reads, W8 and W9 are always directed to the X RAGU,

and W10 and W11 are always directed to the Y AGU.

The Effective Addresses generated (before and after

modification) must, therefore, be valid addresses within

X Data Space for W8 and W9, and Y Data Space for

W10 and W11.

Note:

Register Indirect with Register Offset

Addressing mode is available only for W9 (in

X Data Space) and W11 (in Y Data Space).

In summary, the following addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

4.4.5 OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some

instructions use literal constants of various sizes. For

example, BRA (Branch) instructions use 16-bit signed

literals to specify the Branch destination directly, whereas

the DISI instruction uses a 14-bit unsigned literal field. In

some instructions, such as ULNK, the source of an

operand or result is implied by the opcode itself. Certain

operations, such as a NOP, do not have any operands.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 75

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