S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Software Interface
This section discusses the features and behaviors most relevant to host system software that interacts with S25FL128S and
S25FL256S memory devices.
7. Address Space Maps
7.1 Overview
7.1.1
Extended Address
The S25FL128S and S25FL256S devices support 32-bit addresses to enable higher density devices than allowed by previous
generation (legacy) SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access only 16 Mbytes
(128 Mbits) of maximum density. A 32-bit byte resolution address allows direct addressing of up to a 4 Gbytes (32 Gbits) of address
space.
Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit addresses are
enabled in three ways:
Bank address register — a software (command) loadable internal register that supplies the high order bits of address when
legacy 24-bit addresses are in use.
Extended address mode — a bank address register bit that changes all legacy commands to expect 32 bits of address
supplied from the host system.
New commands — that perform both legacy and new functions, which expect 32-bit address.
The default condition at power-up and after reset, is the Bank address register loaded with zeros and the extended address mode
set for 24-bit addresses. This enables legacy software compatible access to the first 128 Mbits of a device.
The S25FL128S device supports the extended address features in the same way but in essence ignores bits 31 to 24 of any
address because the main flash array only needs 24 bits of address. This enables simple migration from the 128-Mb density to
higher density devices without changing the address handling aspects of software.
7.1.2
Multiple Address Spaces
Many commands operate on the main flash memory array. Some commands operate on address spaces separate from the main
flash array. Each separate address space uses the full 32-bit address but may only define a small portion of the available address
space.
7.2 Flash Memory Array
The main flash array is divided into erase units called sectors. The sectors are organized either as a hybrid combination of 4-kB and
64-kB sectors, or as uniform 256-kbyte sectors. The sector organization depends on the device model selected, see Ordering
Information on page 136.
Table 7.1 S25FL256S Sector and Memory Address Map, Bottom 4-kbyte Sectors
Sector Size (kbyte)
4
64
Sector Count
32
510
Sector Range
SA00
:
SA31
SA32
:
SA541
Address Range
(Byte Address)
00000000h-00000FFFh
:
0001F000h-0001FFFFh
00020000h-0002FFFFh
:
01FF0000h-01FFFFFFh
Notes
Sector Starting Address
—
Sector Ending Address
Document Number: 001-98283 Rev. *I
Page 45 of 144
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