S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
| |||
S25FL128S, S25FL256S
Table 7.7 OTP Address Map
Region
Region 0
Byte Address Range (Hex)
000
...
00F
010 to 013
Region 1
Region 2
...
Region 31
014 to 01F
020 to 03F
040 to 05F
...
3E0 to 3FF
Contents
Least Significant Byte of Spansion Programmed Random
Number
...
Most Significant Byte of Spansion Programmed Random
Number
Region Locking Bits
Byte 10 [bit 0] locks region 0 from programming when = 0
...
Byte 13 [bit 7] locks region 31 from programming when = 0
Reserved for Future Use (RFU)
Available for User Programming
Available for User Programming
Available for User Programming
Available for User Programming
Initial Delivery State (Hex)
Spansion Programmed Random
Number
All bytes = FF
All bytes = FF
All bytes = FF
All bytes = FF
All bytes = FF
All bytes = FF
7.5 Registers
Registers are small groups of memory cells used to configure how the S25FL-S memory device operates or to report the status of
device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used for
each register are noted in each register description. The individual register bits may be volatile, non-volatile, or One Time
Programmable (OTP). The type for each bit is noted in each register description. The default state shown for each bit refers to the
state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is
the value of the bit when the device is shipped from Cypress. Non-volatile bits have the same cycling (erase and program)
endurance as the main flash array.
7.5.1
Status Register 1 (SR1)
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h), Write Disable
(WRDI 04h), Clear Status Register (CLSR 30h).
Table 7.8 Status Register 1 (SR1)
Bits
Field Name
Function
Type
Default State
Description
7
SRWD
Status Register
Write Disable
Non-Volatile
1 = Locks state of SRWD, BP, and configuration register bits when
0
WP# is low by ignoring WRR command
0 = No protection, even when WP# is low
6
P_ERR
Programming Error
Occurred
Volatile, Read only
0
1 = Error occurred.
0 = No Error
5
E_ERR
Erase Error
Occurred
Volatile, Read only
0
1 = Error occurred
0 = No Error
4
BP2
1 if CR1[3]=1,
3
BP1
Block Protection
Volatile if CR1[3]=1, Non-
Volatile if CR1[3]=0
0 when shipped
Protects selected range of sectors (Block) from Program or Erase
2
BP0
from Cypress
1
WEL
Write Enable Latch
Volatile
1 = Device accepts Write Registers (WRR), program or erase
commands
0
0 = Device ignores Write Registers (WRR), program or erase
commands
This bit is not affected by WRR, only WREN and WRDI commands
affect this bit
0
WIP
Write in Progress
Volatile, Read only
1 = Device Busy, a Write Registers (WRR), program, erase or other
0
operation is in progress
0 = Ready Device is in standby mode and can accept commands
The Status Register contains both status and control bits:
Document Number: 001-98283 Rev. *I
Page 48 of 144
Share Link: 