S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
| |||
S25FL128S, S25FL256S
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit is set to 1 and the
WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the Status Register become read-only bits and the
Write Registers (WRR) command is no longer accepted for execution. If WP# is high the SRWD bit and BP bits may be changed by
the WRR command. If SRWD is 0, WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The
SRWD bit has the same non-volatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure indication. When the
Program Error bit is set to a 1 it indicates that there was an error in the last program operation. This bit will also be set when the user
attempts to program within a protected main memory sector or locked OTP region. When the Program Error bit is set to a 1 this bit
can be reset to 0 with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When the Erase Error
bit is set to a 1 it indicates that there was an error in the last erase operation. This bit will also be set when the user attempts to erase
an individual protected main memory sector. The Bulk Erase command will not set E_ERR if a protected sector is found during the
command execution. When the Erase Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register (CLSR)
command. This is a read-only bit and is not affected by the WRR command.
Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected against program
and erase commands. The BP bits are either volatile or non-volatile, depending on the state of the BP non-volatile bit (BPNV) in the
configuration register. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and
erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’s. See Block Protection on page 58
for a description of how the BP bit values select the memory array area protected. The BP bits have the same non-volatile
endurance as the main flash array.
Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to 1 to enable program, write, or erase operations as a means to
provide protection against inadvertent changes to memory or register values. The Write Enable (WREN) command execution sets
the Write Enable Latch to a 1 to allow any program, erase, or write commands to execute afterwards. The Write Disable (WRDI)
command can be used to set the Write Enable Latch to a 0 to prevent all program, erase, and write commands from execution. The
WEL bit is cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the WEL bit may
remain set and should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence,
hardware reset, or software reset, the Write Enable Latch is set to a 0 The WRR command does not affect this bit.
Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation, or any other
operation, during which a new operation command will be ignored. When the bit is set to a 1 the device is busy performing an
operation. While WIP is 1, only Read Status (RDSR1 or RDSR2), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status
Register (CLSR), and Software Reset (RESET) commands may be accepted. ERSP and PGSP will only be accepted if memory
array erase or program operations are in progress. The status register E_ERR and P_ERR bits are updated while WIP = 1. When
P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and unable to receive
new operation commands. A Clear Status Register (CLSR) command must be received to return the device to standby mode. When
the WIP bit is cleared to 0 no operation is in progress. This is a read-only bit.
7.5.2
Configuration Register 1 (CR1)
Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration Register bits can be
changed using the WRR command with sixteen input cycles.
The configuration register controls certain interface and data protection functions.
Document Number: 001-98283 Rev. *I
Page 49 of 144
Share Link: 