UPSD3212C-40U6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212C-40U6

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

uPSD3212A, uPSD3212C, uPSD3212CV

Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)

Symbol

Parameter

Conditions

Min

Max

PT

Aloc

Turbo

Off

Slew

rate(1)

Unit

Maximum Frequency

External Feedback

1/(tS+tCO)

22.2

MHz

fMAX

Maximum Frequency

Internal Feedback (fCNT)

1/(tS+tCO–10)

28.5

MHz

Maximum Frequency

Pipelined Data

1/(tCH+tCL)

40.0

MHz

tS

Input Setup Time

20

+ 4 + 20

ns

tH

Input Hold Time

0

ns

tCH

Clock High Time

Clock Input

15

ns

tCL

Clock Low Time

Clock Input

10

ns

tCO

Clock to Output Delay

Clock Input

25

– 6 ns

tARD

CPLD Array Delay

Any

macrocell

25

+4

ns

tMIN

Minimum Clock Period(2)

tCH+tCL

25

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

2. CLKIN (PD1) tCLCL = tCH + tCL.

Figure 76. Asynchronous RESET / Preset

tARPW

RESET/PRESET

INPUT

REGISTER

OUTPUT

tARP

AI02864

Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)

tCHA

tCLA

CLOCK

tSA tHA

INPUT

REGISTERED

OUTPUT

tCOA

AI02859

147/163

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