UPSD3212C-40U6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
UPSD3212C-40U6
STMicroelectronics
UPSD3212C-40U6 Datasheet PDF : 163 Pages
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uPSD3212A, uPSD3212C, uPSD3212CV
Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(tSA+tCOA)
38.4
fMAXA
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
62.5
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
71.4
tSA
Input Setup Time
7
+2
tHA
Input Hold Time
8
tCHA
Clock Input High Time
9
tCLA
Clock Input Low Time
9
tCOA
Clock to Output Delay
21
tARDA CPLD Array Delay
Any macrocell
11
+2
tMINA
Minimum Clock Period
1/fCNTA
16
Turbo
Off
+ 10
+ 10
+ 10
+ 10
Slew
Rate
–2
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(tSA+tCOA)
21.7
fMAXA
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
27.8
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
33.3
tSA
Input Setup Time
10
+4
tHA
Input Hold Time
12
tCHA
Clock High Time
17
tCLA
Clock Low Time
13
tCOA
Clock to Output Delay
36
tARD
CPLD Array Delay
Any macrocell
25
+4
tMINA
Minimum Clock Period
1/fCNTA
36
Turbo
Off
+ 20
+ 20
+ 20
+ 20
Slew
Rate
–6
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
148/163
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