MSP3400CPP View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

MSP3400CPP

Multistandard Sound Processor

Micronas 

MSP 3400C

4.6. S-Bus Interface

Digital audio information provided by the DMA 2381 via

the AMU is serially transmitted to the MSP 3400C via the

S-Bus. The MSP 3400C is always in S-Bus master

mode.

The S-Bus interface consists of three pins:

1. S_DA_IN:

Four channels (4*16 bits) per sampling cycle (32 kHz)

are transmitted.

2. S_CL:

Gives the timing for the transmission of S-DATA

(4.608 MHz).

3. S_ID:

After 64 S-CLOCK cycles, the S_ID determines the end

of one sampling period.

A detailed timing diagram is shown in Fig. 4–6.

PRELIMINARY DATA SHEET

(Data: MSB first)

H

S-Ident

L

H

S-Clock

L

H

S-Data

L

64 Clock Cycles

16 Bit Sound 1 16 Bit Sound 2 16 Bit Sound 3 16 Bit Sound 4

A

B

Section A

Section B

H

S-Ident

L

H

S-Clock

4.608 MHz L

H

S-Data

L

tS1

tS2

tS4

tS5

LSB of Sound 1

H

S-Ident

L

tS3

H

S-Clock

4.608 MHz L

H

S-Data

MSB of Sound 4

L

Fig. 4–6: S-Bus timing diagram

14

tS6

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