MSP3400CPP View Datasheet(PDF) - Micronas
Part Name
Description
Manufacturer
MSP3400CPP Datasheet PDF : 72 Pages
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PRELIMINARY DATA SHEET
Table 5–3: Control Register
Name
CONTROL
15
RESET
MSP 3400C
14..0
0
5.1. Protocol Description
Write to DFP or Demodulator Part (long protocol)
S
daw
Wait ACK sub-addr ACK addr-byte ACK addr-byte low ACK data-byte high ACK data-byte low ACK P
high
Read from DFP Part (long protocol)
S daw Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S
high
low
dar
ÇÇÇ ÇÇ Wait ACK data-byte ACK data-byte NAK P
ÇÇÇÇÇÇ ÇÇÇÇ high
low
Write to Control / Test / AGC / PLL_Cap Registers (short protocol)
S
daw
Wait ACK
sub-addr
ACK
data-byte high
ACK
data-byte low
ACK P
Read from Control / Test / AGC / PLL_Cap Registers (short protocol)
S
daw
Wait ACK
sub-addr
ACK S
dar
Wait ACK
ÇÇÇÇÇÇ ÇÇÇÇÇÇ data-byte high ACK data-byte low NAK P
Note:
S=
P=
daw =
dar =
ACK =
NAK =
Wait =
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Device Address Write
Device Address Read
Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey)
or master (= CCU, hatched)
Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate
‘End of Read’ or from MSPC indicating internal error state (not illustrated)
I2C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms)
1
I2C_DA
0
S
P
I2C_CL
Fig. 5–1: I2C bus protocol
(MSB first; data must be stable while clock is high)
Micronas
17
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