MSP3400CPP View Datasheet(PDF) - Micronas
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MSP3400CPP Datasheet PDF : 72 Pages
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MSP 3400C
PRELIMINARY DATA SHEET
5. I2C Bus Interface: Device and Subaddresses
As a slave receiver, the MSP 3400C can be controlled
via I2C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator part and
the audio processor part (DFP) have two separate sub-
addressing register banks.
In order to allow for more MSP 3400C ICs to be con-
nected to the control bus, an ADR_SEL pin has been im-
plemented. With ADR_SEL pulled to high, the MSP
3400C responds to changed device addresses, thus two
identical devices can be selected. Other devices of the
same family will have different subaddresses (e.g. 34x0)
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
The IC is selected by asserting a special device address
in the address part of an I2C transmission. A device ad-
dress pair is defined as a write address (80 hex or 84
hex) and a read address (81 hex or 85 hex). Writing is
done by sending the device write address first, followed
by the subaddress byte, two address bytes, and two
data bytes. For reading, the read address has to be
transmitted first by sending the device write address (80
hex or 84 hex), followed by the subaddress byte, and two
address bytes. Without sending a stop condition, read-
ing of the addressed data is done by sending the device
read address (81 hex or 85 hex) and reading two bytes
Table 5–1: I2C Bus Device Addresses
of data. Refer to Fig. 5–1 I2C Bus Protocol and section
5.2. Proposal for MSP 3400C I2C Telegrams.
Due to the internal architecture of the MSP 3400C, the
IC cannot react immediately to an I2C request. The typi-
cal response time is about 0.3 ms. If the addressed pro-
cessor is not ready for further transmissions on the I2C
bus, the clock line I2C_CL is pulled low. This puts the
current transmission into a wait state. After a certain pe-
riod of time, the MSP 3400C releases the clock, and the
interrupted transmission is carried on.
The I2C Bus lines can be set tristate by switching the IC
into “Standby”-mode.
I2C-Bus error conditions:
In case of any internal error, the MSP’s wait-period is ex-
tended to 1.77 ms. Afterwards, the MSP does not ac-
knowledge (NAK) the device address. The data line will
be left HIGH by the MSP, and the clock line will be re-
leased. The master can then generate a STOP condition
to abort the transfer.
By means of NAK, the master is able to recognize the er-
ror state and to reset the IC via I2C-Bus. While transmit-
ting the reset protocol (section. 5.2.4.) to ‘CONTROL’,
the master must ignore the not acknowledge bits (NAK)
of the MSP.
A detailed timing diagram is shown in Fig. 5–1 and
Fig. 5–2.
ADR_SEL
Mode
MSP device address
Low
Write
Read
80 hex
81 hex
High
Write
Read
84 hex
85 hex
Left Open
Write
Read
88 hex
89 hex
Table 5–2: I2C Bus Device and Subaddresses
Name
CONTROL
TEST1
TEST2
WR_DEM
RD_DEM
WR_DFP
RD_DFP
AGC
PLL_CAP
Binary Value
0000 0000
0000 0001
0000 0010
0001 0000
0001 0001
0001 0010
0001 0011
0001 1110
0001 1111
Hex Value
00
01
02
10
11
12
13
1E
1F
Function
software reset
only for internal use
only for internal use
write address demodulator
read address demodulator
write address DFP
read address DFP
read AGC RMS
read / write PLL_Cap
16
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