MSP3400CPP View Datasheet(PDF) - Micronas
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MSP3400CPP Datasheet PDF : 72 Pages
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PRELIMINARY DATA SHEET
MSP 3400C
4.7. I2S Bus Interface
By means of this standardized interface, additional fea-
ture processors can be connected to the MSP 3400C.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word bound-
aries. The so-called PHILIPS format, which is character-
ized by a change of the I2S_WS signal, one I2S_CL peri-
od before the word boundaries, is selected by setting
MODE_REG[4]=1.
The MSP 3400C normally serves as the master on the
I2S interface. Here, the clock and word strobe lines are
driven by the MSP 3400C. By setting MODE_REG[3]=1,
the MSP 3400C is switched to a slave mode. Now, these
lines are input to the MSP 3400 C, and the master clock
is synchronized to 576 times the I2S_WS rate (32 kHz).
No D2MAC operation is possible in this mode.
The I2S bus interface consists of five pins:
1. I2S_DA_IN1:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
2. I2S_DA_IN2:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
3. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
4. I2S_CL:
Gives the timing for the transmission of I2S serial data
(1.024 MHz).
5. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.
A detailed timing diagram is shown in Fig. 4–7.
(Data: MSB first)
I2S_WS
FI2SWS
SONY Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODE_REG[4]
I2S_CL
I2S_DAIN R LSB L MSB
Detail A
16 bit left channel
I2S_DAOUT R LSB L MSB
Detail B
16 bit left channel
SONY Mode
PHILIPS Mode
Detail C
L LSB R MSB
L LSB R MSB
16 bit right channel
16 bit right channel
R LSB L LSB
R LSB L LSB
Detail C
I2S_CL
FI2SCL
TI2SWS1
TI2SWS2
I2S_WS as INPUT
TI2S5
TI2S6
I2S_WS as OUTPUT
Fig. 4–7: I2S Bus timing diagram
Micronas
Detail A,B
I2S_CL
I2S_DA_IN
I2S_DA_OUT
TI2S1
TI2S3
TI2S2
TI2S4
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