ISL8200AMMREP View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL8200AMMREP Datasheet PDF : 24 Pages
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ISL8200AMM
Applications Information
Programming the Output Voltage (RSET)
The ISL8200AMMREP has an internal 0.6V ± 0.7% reference
voltage. Programming the output voltage requires a dividing
resistor (RSET) between the VOUT_SET pin and the VOUT
regulation point. The output voltage can be calculated as shown
in Equation 1:
VOUT
=
0.6
1
+
-R-R---S-O--E--S-T-
(EQ. 1)
Note: ISL8200AMMREP has integrated 2.2kΩ resistances into
the module dividing resistor for the bottom side (ROS). The
resistances for different output voltages in single phase
operation are listed in Table 1. For a parallel setup, please refer
to the current sharing application note (Coming Soon).
VOUT
RSET
TABLE 1. VOUT - RSET
0.6V
0.8V
0Ω
732Ω
1.0V
1.47kΩ
1.2V
2.2kΩ
VOUT
RSET
1.5V
3.32kΩ
1.8V
4.42kΩ
2.0V
5.11kΩ
2.5V
6.98kΩ
VOUT
RSET
3.3V
10kΩ
5.0V
16.2kΩ
6.0V
20kΩ
The output voltage accuracy can be improved by maintaining the
impedance at VOUTSET (internal VSEN1+) at or below 1kΩ
effective impedance. Note: the impedance between VSEN1+ and
VSEN1- is about 500k.
The module has a minimum input voltage at a given output
voltage, which needs to be a minimum of 1.43 times the output
voltage if operating at fSW = 700kHz switching frequency. This is
due to the Minimum PWM OFF Time (tMIN-OFF).
The equation to determine the minimum PVIN to support the
required VOUT is given by Equations 2 and 3; it is recommended
to add 0.5V to the result to account for temperature variations.
PVIN_MIN = -t--S---VW---O---–-U---T-t--M-----I-tN--S--_--W-O---F---F-
(EQ. 2)
tSW = switching period = 1/fSW
for the 700kHz switching frequency = 1428ns
PVIN_MIN = 1.43 VOUT
(EQ. 3)
For 3V input voltage operation, the VIN voltage should be at least
4.5V for sufficient gate drive voltage. This can be accomplished
by using a voltage greater than or equal to 4.5V on VIN. VIN is the
input to the internal LDO that powers the control circuitry. PVIN is
the power input to the power stage. Figure 21 shows a scenario
where the power stage is running down to 3.0V and the control
circuitry is running down to 4.5V. Figure 22 is a more general
setup and can accommodate a VIN range from 4.5V up to 20V.
VIN = 4.5V TO 20V
PVIN = 3V TO 20V
PVIN
VIN
VOUT
ISL8200AMMREP
POWER MODULE
EN
VOUT_SET
FF
VSEN_REM-
ISHARE
PGND1
10µF
5k
FIGURE 21. 3V OPERATION
VIN = 4.5V TO 20V
PVIN
VIN
VOUT
ISL8200AMMREP
POWER MODULE
EN
VOUT_SET
FF
VSEN_REM-
ISHARE
PGND1
10µF
5k
FIGURE 22. 4.5V TO 20V OPERATION
Selection of the Input Capacitor
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, but consideration should be
taken for the higher surge current during power-up. The
ISL8200AMMREP provides the soft-start function that controls
and limits the current surge. The value of the input capacitor can
be calculated by Equation 4:
CINMIN
=
IO
------D------------1-----–-----D-----------
VP-PMAX FS
(EQ. 4)
Where:
CIN(MIN) is the minimum input capacitance (µF) required
IO is the output current (A)
D is the duty cycle (VO/VIN)
VP-P(MAX) is the maximum peak-to-peak voltage (V)
FS is the switching frequency (Hz)
In addition to the bulk capacitance, some low Equivalent Series
Inductance (ESL) ceramic capacitance is recommended to
decouple between the PVIN pin and PGND pin. This is used to
reduce the voltage ringing created by the switching current
across parasitic circuit elements.
FN8287 Rev 2.00
June 3, 2015
Page 13 of 24
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