ISL8200AMMREP View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL8200AMMREP Datasheet PDF : 24 Pages
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ISL8200AMM
Frequency Synchronization and Phase Lock
Loop
The FSYNC_IN pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (RFS) to PGND1 from the FSYNC_IN pin, the switching
frequency can be set at any frequency between 700kHz and
1.5MHz. The ISL8200AMMREP has an integrated 59kΩ resistor
between FSYNC_IN and PGND1, which sets the default frequency
to 700kHz. The frequency setting curve shown in Figure 34 is
provided to assist in selecting an externally connected resistor
RFS-ext between FSYNC_IN and PGND1 to increase the switching
frequency.
1500
1400
1300
1200
1100
1000
900
800
700
0
100
200
300
400
RFS-ext (kΩ)
FIGURE 34. RFS-ext vs SWITCHING FREQUENCY
By connecting the FSYNC_IN pin to an external square pulse
waveform (such as the CLKOUT signal, typically 50% duty cycle
from another ISL8200AMMREP), the ISL8200AMMREP will
synchronize its switching frequency to the fundamental
frequency of the input waveform. The voltage range on the
FSYNC_IN pin is VCC/2 to VCC. The Frequency Synchronization
feature will synchronize the leading edge of the CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal. CLKOUT is
not available until the PLL locks.
The locking time is typically 210µs for fSW = 700kHz. EN is not
released for a soft-start cycle until FSYNC_IN is stabilized and the
PLL is in locking. It is recommended to connect all EN pins
together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles causes
the IC to be disabled until the PLL returns locking, at which point
a soft-start cycle is initiated and normal operation resumes.
Holding FSYNC_IN low will disable the IC.
Setting Relative Phase-Shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by the VCC
resistor divider output, the ISL8200AMMREP operates with
CLKOUT phase shifted, as shown in Table 2. The phase shift is
latched as VCC raises above POR so it cannot be changed on the
fly.
DECODING
PH_CNTRL RANGE
<29% of VCC
29% to 45% of VCC
45% to 62% of VCC
62% to VCC
TABLE 2.
PHASE FOR CLKOUT WRT
CHANNEL 1
-60°
90°
120°
180°
REQUIRED
PH_CNTRL
15% VCC
37% VCC
53% VCC
VCC
Layout Guide
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary, which
are illustrated in Figures 35 and 36.
• The ground connection between PGND1 (pin 15) and PGND
(pin 18) should be a solid ground plane under the module.
• Place a high frequency ceramic capacitor between (1) PVIN
and PGND (pin 18) and (2) a 10µF between PVCC and PGND1
(pin 15) as close to the module as possible to minimize high
frequency noise. High frequency ceramic capacitors close to
the module between VOUT and PGND will help to minimize
noise at the output ripple.
• Use large copper areas for power path (PVIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
• Keep the trace connection to the feedback resistor short.
• Use remote sensed traces to the regulation point to achieve a
tight output voltage regulation, and keep them in parallel.
Route a trace from VSEN_REM- to a location near the load
ground, and a trace from feedback resistor to the point-of-load
where the tight output voltage is desire.
• Avoid routing any sensitive signal traces, such as the VOUT and
VSENREM- sensing point near the PHASE pin or any other
noise-prone areas.
• FSYNC_IN is a sensitive pin. If it is not used for receiving an
external synchronization signal, then keep the trace
connecting to the pin short. A bypass capacitor value of 100pF,
connecting between FSYNC_IN pin and GND1, can help to
bypass the noise sensitivity on the pin.
FN8287 Rev 2.00
June 3, 2015
Page 18 of 24
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