ISL8200AMMREP View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL8200AMMREP Datasheet PDF : 24 Pages
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ISL8200AMM
3.5
3.0
2.5
3.3V
2.0
1.5V
1.5
0.8V
1.0
0.5
0.0
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 37. POWER LOSS vs LOAD CURRENT (5VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
12
10
8
3.3V
6
1.5V
0.8V
4
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 38. DERATING CURVE (5VIN) 0 LFM FOR VARIOUS
OUTPUT VOLTAGES
5.0
4.5
4.0
5.0V
3.5
3.3V
3.0
2.5V
2.5
1.5V
2.0
0.8V
1.5
1.0
0.5
0.0
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 39. POWER LOSS vs LOAD CURRENT (12VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
12
10
8 5.0V
3.3V
6
2.5V
1.5V
4
0.8V
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 40. DERATING CURVE (12VIN) 0 LFM FOR VARIOUS
OUTPUT VOLTAGES
Thermal Considerations
Empirical power loss curves, shown in Figures 37 to 40, along
with JA from thermal modeling analysis can be used to evaluate
the thermal consideration for the module. The derating curves
are derived from the maximum power allowed while maintaining
the temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
The structure of the ISL8200AMMREP belongs to the Quad Flat-
pack No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical conductivity, low
weight and small size. The QFN package is applicable for surface
mounting technology and is being more readily used in the
industry. The ISL8200AMMREP contains several types of devices,
including resistors, capacitors, inductors and control ICs. The
ISL8200AMMREP is a copper lead-frame based package with
exposed copper thermal pads, which have good electrical and
thermal conductivity. The copper lead frame and multi component
assembly is overmolded with polymer mold compound to protect
these devices.
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing L23.15x15 on page 23. The module has a small size of
15mm x 15mm x 2.2mm. Figure 41 shows typical reflow profile
parameters. These guidelines are general design rules. Users
could modify parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8200AMMREP is a lead-frame footprint, which
is attached to the PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing
L23.15x15 on page 23. The PCB layout pattern is essentially 1:1
with the QFN exposed pad and I/O termination dimensions,
except for the PCB lands being a slightly extended distance of
0.2mm (0.4mm max) longer than the QFN terminations, which
allows for solder filleting around the periphery of the package.
This ensures a more complete and inspectable solder joint. The
thermal lands on the PCB layout should match 1:1 with the
package exposed die pads.
FN8287 Rev 2.00
June 3, 2015
Page 20 of 24
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