T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC
characteristics for the SATA interface.
Table 93. Gen2i/2m 3 G receiver input DC specifications (SVDD = 1.0 V)3
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
VSATA_RXDIFF
240
-
750
mV p-p
1
Differential receiver input impedance ZSATA_RXSEIM 85
100
115
Ω
2
OOB signal detection threshold
VSATA_OOB
75
120
240
mV p-p
2
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
3. For recommended operating conditions, see Table 3.
3.19.8.2 SATA AC timing specifications
This section discusses the SATA AC timing specifications.
3.19.8.2.1 AC requirements for SATA REF_CLK
The AC requirements for the SATA reference clock listed in this table are to be
guaranteed by the customer's application design.
Table 94. SATA reference clock input requirements6
Parameter
Symbol
Min
Typ
Max
Unit
Notes
SDn_REF_CLKn_P/SDn_REF_CLKn_N
frequency range
tCLK_REF
-
100/125 -
MHz
1
SDn_REF_CLKn_P/SDn_REF_CLKn_N clock tCLK_TOL -350
-
frequency tolerance
+350
ppm
-
SDn_REF_CLKn_P/SDn_REF_CLKn_N
tCLK_DUTY 40
50
60
%
5
reference clock duty cycle
SDn_REF_CLKn_P/SDn_REF_CLKn_N cycle- tCLK_CJ
-
-
100
ps
2
to-cycle clock jitter (period jitter)
SDn_REF_CLKn_P/SDn_REF_CLKn_N total tCLK_PJ
-50
-
reference clock jitter, phase jitter (peak-to-peak)
+50
ps
2, 3, 4
Notes:
1. Caution: Only 100 and 125MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.
5. Measurement taken from differential waveform
6. For recommended operating conditions, see Table 3.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
131
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