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ST72361J4-AUTO View Datasheet(PDF) - STMicroelectronics

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ST72361J4-AUTO Datasheet PDF : 279 Pages
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Electrical characteristics
ST72361xx-Auto
19.5.2
PLL characteristics
Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C(a) or VDD 4.5 to 5.5V @ TA -40 to
125°C
Table 97. PLL characteristics
Symbol
Parameter
Conditions
Min
TA = 0 to +70°C
3.8
VDD(PLL) PLL Voltage Range TA = -40 to +125°C
4.5
fOSC
PLL input frequency
range
2
fCPU/fCPU PLL jitter(1)
fOSC = 4 MHz, VDD = 4.5 to
5.5V
fOSC = 2 MHz, VDD = 4.5 to
5.5V
1. Data characterized but not tested.
2. Under characterization.
Typ Max Unit
5.5
4 MHz
See note(2)
%
Figure 101. PLL jitter vs signal frequency(1)
0.8
0.7
0.6
PLL ON
0.5
PLL OFF
0.4
0.3
0.2
0.1
0
2000
1000
500
250
125
Application Signal Frequency (KHz)
1. Measurement conditions: fCPU = 4 MHz, TA = 25°C
The user must take the PLL jitter into account in the application (for example in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore, the longer the period of the
application signal, the less it is impacted by the PLL jitter.
Figure 124 shows the PLL jitter integrated on application signals in the range 125 kHz to
2 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
a. Data characterized but not tested
236/279
Doc ID 12468 Rev 3

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