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ST72361J4-AUTO View Datasheet(PDF) - STMicroelectronics

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ST72361J4-AUTO Datasheet PDF : 279 Pages
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Electrical characteristics
Figure 118. SPI master timing diagram
SS INPUT
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
MISO INPUT
tc(SCK)
tsu(MI)
th(MI)
ttww((SSCCKKHL))
MSB IN
tv(MO)
BIT6 IN
MOSI OUTPUT See note 2
MSB OUT
BIT6 OUT
ST72361xx-Auto
ttrf((SSCCKK))
th(MO)
LSB IN
LSB OUT
See note 2
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
19.13 10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 113. ADC characteristics
Symbol
Parameter
Conditions
fADC
VAIN
RAIN
CAIN
fAIN
ADC clock frequency
Conversion voltage range(2)
External input impedance
External capacitor on analog
input
Variation frequency of analog
input signal
Ilkg
CADC
tCONV
Negative input leakage current VIN VSS, | IIN | < 400µA
on robust analog pins (refer to on adjacent robust
Table 3)
analog pin
Internal sample and hold
capacitor
Conversion time
fADC = 4 MHz
IADC
Analog part
Digital part
Sunk on VDDA2)
Sunk on VDD
Min(1)
0.4
VSSA
Typ Max(1)
4
VDDA
see
Figure 142
and
Figure 143
Unit
MHz
V
k
pF
Hz
5
6
µA
6
3.5
14
3.6
0.2
pF
µs
1/fADC
mA
252/279
Doc ID 12468 Rev 3

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