STM32WB55CEV7 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32WB55CEV7
STMicroelectronics
STM32WB55CEV7 Datasheet PDF : 193 Pages
| |||
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 90. IWDG min/max timeout period at 32 kHz (LSI1)(1)
Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit
/4
0
/8
1
/16
2
/32
3
/64
4
/128
5
/256
6 or 7
0.125
0.250
0.500
1.0
2.0
4.0
8.0
512
1024
2048
4096
ms
8192
16384
32768
1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.
6.3.28
6.3.29
Clock recovery system (CRS)
The devices embed a special block for the automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range.
This automatic trimming is based on the external synchronization signal, which can be
derived from USB Sart Of Frame (SOF) signalization, from LSE oscillator, from an external
signal on CRS_SYNC pin or generated by user software.
For faster lock-in during startup it is also possible to combine automatic trimming with
manual trimming action.
Communication interfaces characteristics
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
ï‚· Standard-mode (Sm): bit rate up to 100 kbit/s
ï‚· Fast-mode (Fm): bit rate up to 400 kbit/s
ï‚· Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.
Table 91. Minimum I2CCLK frequency in all I2C modes
Symbol Parameter
Condition
Min
Unit
Standard-mode
-
2
Analog filter ON, DNF = 0
9
f(I2CCLK)
I2CCLK
frequency
Fast-mode
Analog filter OFF, DNF = 1
9
Analog filter ON, DNF = 0
19
Fast-mode Plus
Analog filter OFF, DNF = 1
16
MHz
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (see the reference manual).
158/193
DS11929 Rev 10
Share Link: 