CL-PS7500FE データシートの表示（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
Read
Reset
bit[2] bank 2 DRAM width
0
32-bit
1
16-bit
bit[1] bank 1 DRAM width
0
32-bit
1
16-bit
bit[0] bank 0 DRAM width
0
32-bit
1
16-bit
reads above values
set bits to zero (32-bit)
9.2.4 EDO and Timing Mode Selection
76543210
XPRESSSS
The DRAMCR at address 0x032000D0 also controls EDO mode and some other timing features. On reset
all these bits are set low, that is, inactive. To ensure reliable operation in many systems after reset, these
register bits must be correctly programmed before the DRAM is used.
Write:
P
R
E
Read
Reset
Precharge RAS control
0
3 MEMCLK cycles minimum RAS precharge
1
4 MEMCLK cycles minimum RAS precharge
RAS to CAS delay
0
2 MEMCLK cycles RAS to CAS delay on reads
1
3 MEMCLK cycles RAS to CAS delay on reads
EDO Control
0
Fast Page DRAMs selected
1
EDO DRAMs selected
reads above values
set all bits to zero (Fast page, no extra delays)
To take advantage of the faster page mode accesses of EDO DRAMs, the memory clock frequency
should be increased accordingly. For example, a system using 80-ns Fast Page DRAMs require a memory
clock of ~32 MHz; 80-ns EDO DRAMs could use a memory clock of ~50 MHz. This improves the asymp-
totic DRAM bandwidth from 64 to 100 Mbytes for a 32-bit-wide system.
However, the increase in memory clock may cause the Trac time and the Trp times to be violated at 4 and
3 MEMCLK cycles respectively (when EDO selected). The register configuration bits R and P allow each
of these to be increased by one MEMCLK cycle when appropriate.
16-bit Mode
In 16-bit mode CL-PS7500FE must perform two reads or writes for each 32-bit word DRAM access
requested by the ARM processor or the DMA controller. Only nCAS[1] and nCAS[0] are used, to access
the two bytes of each word. nCAS[3:2] are held at logic one. In 16-bit mode, the same number of physical
June 1997
ADVANCE DATA BOOK v2.0
71
MEMORY SUBSYSTEMS
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