CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

To preserve minimum RAS precharge times when one access closely follows another to the same DRAM

bank, the following must be added to these values

if bit 7 is low

0 or 1 cycles

if bit 7 is high

0, 1, or 2 cycles

9.3 DMA Channels

The CL-PS7500FE supports video, cursor and sound DMA to enable direct transfer of qwords of data

from DRAM to the video and sound processing interfaces. All DMA is in units of four words (qwords) and

data can be read from any of the four banks of DRAM in either 16- or 32-bit mode. CL-PS7500FE contains

a DMA address generator that has a number of programmable control registers associated with each

channel. Most of these registers contain 28-bit physical addresses. The DMA controller also includes sup-

port for DMA to dual-panel LCD screens.

All three of the DMA channels have at least one CURRENT register that contains the address in memory

of the next data to be fetched from DRAM on that channel. Each channel uses START, INIT, and END

registers to define the size and location of the buffer in memory where DMA occurs. However, all three

channels have slightly different methods of using these registers. Exact details of the contents of all these

registers can be found in Chapter 10, “MEMORY AND I/O PROGRAMMERS’ MODEL”.

9.3.1 Video DMA

The video DMA channel can be used in two modes. Duplex mode fetches DMA data for use with a dual-

panel LCD display, and involves fetching a qword of data for the top half of the display, followed by a qword

of data for the bottom half of the display, then the next qword for the top half and so on. This is imple-

mented using two parallel sets of registers that must be programmed accordingly. A description of how to

use the CL-PS7500FE with a dual panel LCD display can be found in Appendix B, “Dual-Panel

Liquid Crystal Displays”.

Normal mode is used for standard CRT and LCD displays and data is fetched sequentially from the frame

buffer. Selection between normal and duplex mode of operation is achieved through VIDCR[7] at location

0x032001E0. VIDCR[5] enables the video DMA channel and should not be enabled until the other

address registers are programmed to sensible values.

The registers associated with video DMA should only be programmed during the FLYBACK period, to

avoid corrupting data while DMA is in progress or while the display is half way through a raster. The state

of the internal FLYBACK signal is available for polling in the IOCR, and can create an interrupt by pro-

gramming the IRQA mask register appropriately.

There is a single VIDSTART register that should be programmed with the location in memory of the first

qword of video data at the start of the frame buffer. The VIDEND register is programmed with the location

in memory of the start of the last qword in the frame buffer image.

For normal mode operation, the VIDINITA register should be programmed with the address in memory of

the data that creates the pixels at the top-left corner of the display. This need not necessarily be at the

same address as that programmed into the VIDSTART register, thus allowing hardware scrolling by mov-

ing the address in the VIDINITA register through the frame buffer. The value in the VIDINITA register is

automatically transferred into the VIDCURA register during the FLYBACK period, so there is no need to

program the current register separately.

74

MEMORY SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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