CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

9.2.6 DRAM Self-Refresh

76543210

CCCCRRRR

The nCAS and nRAS lines can be forced active by programming bits in the SELFREF register at address

0x032000D4. This is intended for use with self refresh DRAM, and particularly in conjunction with STOP

mode so that DRAM can retain state when all the CL-PS7500FE clocks have been stopped. All DMA must

be stopped and the code that writes to this register must be executing from ROM.

C

R

Write

Read

Reset

force all nCAS low

force all nRAS low

bits[7:4]

0

normal

1

force to zero

bits[3:0]

0

normal

1

force to zero

reads above values

set bits to zero (normal)

9.2.7 Non-Sequential Access Time and RAS Precharge

At the end of one DRAM access, the earliest the next access can start is two memory clock cycles later.

The new access must be to a different DRAM bank than the previous for this to be allowed. If the new

access is to the same bank as the previous, to maintain the RAS precharge time (tRP), an extra clock cycle

is inserted before the nRAS[x] signal is asserted again.

Thus, the minimum RAS precharge time is guaranteed to be 3 MEMCLK cycles. This can be increased

to 4 MEMCLK cycles by setting DRAMCR[7] high. These wait states increase the access time of a non-

sequential DRAM access by 1 or 2 cycles.

To provide adequate RAS access delay (tRAC) at higher memory clock frequencies, DRAMCR[6] can be

set. This inserts a wait state between the falling nRAS and the first falling nCAS of a read cycle.

Setting bit 5 of the DRAMCR delays the latching of data into CL-PS7500FE by one cycle to support EDO

DRAMs and so increases non-sequential access time by one cycle.

Table 9-1 shows how to calculate the non-sequential DRAM read access time:

Table 9-1. Non-Sequential DRAM Read Access Times

DRAMCR

Fast Page (bit 5 = 0)

EDO (bit 5 = 1)

Bit 6 = 0 Bit 6 = 1

5

6

6

7

The non-sequential write access remains at 5 cycles for the above conditions.

June 1997

ADVANCE DATA BOOK v2.0

73

MEMORY SUBSYSTEMS

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