CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

addresses are available as for 32-bit mode, meaning that only 32 Mbytes of DRAM is supported per bank.

Words are stored in DRAM with the upper half-word at the lower address.

CONTENTS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 00 0 0

ADDRESS

0X10000000

1111111111111111

0X10000001

When this is read, the ARM sees:

MSB

LSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000 1111111111111111

In 16-bit mode, byte reads and writes only require a single DRAM access, and the LSB of the column

address is decoded in conjunction with the nCAS[1:0] outputs to select a single byte from four. For this

reason byte reads and writes for 16-bit-wide DRAMs have the same timing as for the non-sequential 32-

bit case.

16-bit mode word accesses involve a non-sequential access for the upper halfword, followed by a sequen-

tial access for the lower half word at the next memory location. A non sequential 16-bit mode word access

thus requires 7 MEMCLK cycles, then sequential accesses can continue until a page boundary is

reached, taking two cycles for each half word.

9.2.5 DRAM Refresh

DRAM refresh is controlled by a small state machine and counter within CL-PS7500FE. The refresh inter-

val timer is clocked by a clock derived from the fixed frequency I_OCLK, and thus the refresh intervals

remain the same even if the frequency of MEMCLK is increased for use with faster DRAM. There are four

timings available for refresh, controlled by the REFCR refresh control register at address 0x0320008C.

During reset, the refresh timer is reset to the fastest value (16 µs), and the counter and state machine are

clocked such that refresh continues even during reset.

76 5 4 3 2 1 0

XXXXRRRR

R

Write

Read

Reset

refresh period

bit[3:0]

0000 refresh off

0001 16 µs

0010 32 µs

0100 64 µs

1000 128 µs

all others are undefined

return above values

set to ‘0001’ (fastest available refresh rate)

72

MEMORY SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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