ST72F324K4TCRE データシートの表示（PDF） - STMicroelectronics

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ST72F324K4TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Figure 49. Single master/single slave application

MSB

Master

LSB

8-bit Shift Register

MISO

MOSI

MISO

MOSI

MSB

Slave

LSB

8-bit Shift Register

SPI

clock

generator

SCK

SS +5V

SCK

SS

Not used if SS is managed

by software

ct(s) Slave Select management

du As an alternative to using the SS pin to control the Slave Select signal, the application can

ro choose to manage the Slave Select signal by software. This is configured by the SSM bit in

P the SPICSR register (see Figure 51).

te In software management, the external SS pin is free for other application uses and the

le internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

o In Master mode:

bs – SS internal must be held high continuously

O Depending on the data/clock timing relationship, there are two cases in Slave mode (see

) - Figure 50):

t(s If CPHA = 1 (data latched on second clock edge):

c – SS internal must be held low during the entire transmission. This implies that in

du single slave applications the SS pin either can be tied to VSS, or made free for

ro standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in

the in the SPICSR register)

P If CPHA = 0 (data latched on first clock edge):

lete– SS internal must be held low during byte transmission and pulled high between

each byte to allow the slave to write to the shift register. If SS is not pulled high, a

so Write Collision error will occur when the slave writes to the shift register (see Write

Ob collision error (WCOL) on page 104).

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Doc ID 13841 Rev 1

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