ST72F324K4TCRE データシートの表示（PDF） - STMicroelectronics

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ST72F324K4TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

10.4.2 Main features

● Full duplex synchronous transfers (on 3 lines)

● Simplex synchronous transfers (on 2 lines)

● Master or slave operation

● 6 master mode frequencies (fCPU/4 max.)

● fCPU/2 max. slave mode frequency (see note)

● SS Management by software or hardware

● Programmable clock polarity and phase

● End of transfer interrupt flag

) Note:

Obsolete Product(s) - Obsolete Product(s 10.4.3

● Write collision, Master mode fault and Overrun flags

In slave mode, continuous transmission is not possible at maximum frequency due to the

software overhead for clearing status flags and to initiate the next transmission sequence.

General description

Figure 48 shows the serial peripheral interface (SPI) block diagram. The SPI has three

registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through four pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and input by SPI slaves

– SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master

communicate with slaves individually and to avoid contention on the data lines.

Slave SS inputs can be driven by standard I/O ports on the master MCU.

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Doc ID 13841 Rev 1

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