ST72F324K4TCRE データシートの表示（PDF） - STMicroelectronics

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ST72F324K4TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

M

Table 51. CSR register description

Bit Name

Function

Input Capture Flag 1

7 ICF1

0: No Input Capture (reset value).

1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

Output Compare Flag 1

0: No match (reset value).

6 OCF1 1: The content of the free running counter has matched the content of the OC1R

register. To clear this bit, first read the SR register, then read or write the low byte of

the OC1R (OC1LR) register.

) Timer Overflow Flag

uct(s 5 TOF

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

d Note: Reading or writing the ACLR register does not clear TOF.

ro Input Capture Flag 2

lete P 4 ICF2

0: No input capture (reset value).

1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

register, then read or write the low byte of the IC2R (IC2LR) register.

o Output Compare Flag 2

- Obs 3 OCF2

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R

register. To clear this bit, first read the SR register, then read or write the low byte of

the OC2R (OC2LR) register.

t(s) Timer Disable

Produc 2 TIMD

This bit is set and cleared by software. When set, it freezes the timer prescaler and

counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce

power consumption. Access to the timer registers is still available, allowing the timer

configuration to be changed, or the counter reset, while it is disabled.

0: Timer enabled.

1: Timer prescaler, counter and outputs disabled.

te1:0 - Reserved, must be kept cleared.

soleInput Capture 1 High Register (IC1HR)

Ob This is an 8-bit register that contains the high part of the counter value (transferred by the

input capture 1 event).

IC1HR

Reset value: undefined

7

6

5

4

3

2

1

0

MSB

LSB

RO

RO

RO

RO

RO

RO

RO

RO

Doc ID 13841 Rev 1

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