ST72F324K4TCRE データシートの表示（PDF） - STMicroelectronics
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ST72F324K4TCRE
STMicroelectronics
ST72F324K4TCRE Datasheet PDF : 194 Pages
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ST72324xx-Auto
On-chip peripherals
Table 52. 16-bit timer register map and reset values (continued)
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
Timer A: 33 CSR
ICF1
OCF1
TOF ICF2(2) OCF2(2) TIMD
-
-
Timer B: 43 Reset value
x
x
x
x
x
0
x
x
Timer A: 34 IC1HR
MSB
LSB
Timer B: 44 Reset value
x
x
x
x
x
x
x
x
Timer A: 35 IC1LR
MSB
LSB
Timer B: 45 Reset value
x
x
x
x
x
x
x
x
Timer A: 36 OC1HR
MSB
LSB
Timer B: 46 Reset value
1
0
0
0
0
0
0
0
) Timer A: 37 OC1LR
MSB
LSB
t(s Timer B: 47 Reset value
0
0
0
0
0
0
0
0
c Timer A: 3E(3) OC2HR
MSB
LSB
u Timer B: 4E Reset value
1
0
0
0
0
0
0
0
d Timer A: 3F(3) OC2LR
MSB
LSB
ro Timer B: 4F Reset value
0
0
0
0
0
0
0
0
P Timer A: 38 CHR
MSB
LSB
te Timer B: 48 Reset value
1
1
1
1
1
1
1
1
le Timer A: 39 CLR
MSB
LSB
o Timer B: 49 Reset value
1
1
1
1
1
1
0
0
bs Timer A: 3A ACHR
MSB
LSB
O Timer B: 4A Reset value
1
1
1
1
1
1
1
1
- Timer A: 3B ACLR
MSB
LSB
t(s) Timer B: 4B Reset value
1
1
1
1
1
1
0
0
c Timer A: 3C(4) IC2HR
MSB
LSB
u Timer B: 4C Reset value
x
x
x
x
x
x
x
x
d Timer A: 3D(4) IC2LR
MSB
LSB
ro Timer B: 4D Reset value
x
x
x
x
x
x
x
x
P 1. In Flash devices, these bits are not used in Timer A and must be kept cleared.
te 2. In Flash devices, these bits are forced by hardware to 0 in Timer A.
le 3. In Flash devices, the TAOC2HR and TAOC2LR registers are write only; reading them will return undefined values.
Obso 4. In Flash devices, the TAIC2HR and TAIC2LR registers are not present.
10.4 Serial peripheral interface (SPI)
10.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface cannot be a master in a multi-master system.
Doc ID 13841 Rev 1
97/193
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