STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

Table 4-4. RAMDAC DC Specification

Symbol

Vref_dac

INL

DNL

BLC

WLC

Parameter

Voltage Reference

Integrated Non Linear Error

Differentiated Non Linear Error

Black Level Current

White Level Current

Min

1.00 V

-

-

1.0 mA

15.00 mA

Max

1.24 V

3 LSB

1 LSB

2.0 mA

18.50 mA

Table 4-5. VGA RAMDAC Power Consumption

DCLK

(MHz)

-

6.25 - 135

DAC mode

(State)

Shutdown

Active

PMax (mW)

VDD_DAC = 2.45V

VDD_DAC = 2.7V

0

0

150

180

Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC)

t(s) HCLK

(MHz)

CPUCLK

(MHz)

MCLK

(MHz)

duc 66

133 (x2)

66

lete Pro 66

133 (x2)

90

Mode

SYNC

ASYNC

DCLK

(MHz)

Stopped

135

Stopped

135

PMU

(State)

Stop Clock

Full Speed

Stop Clock

Full Speed

Stop Clock

Full Speed

Stop Clock

Full Speed

PMax (W)

V2.5V=2.45V

V2.5V=2.7V

1.5

1.9

2.5

3.0

2.1

2.6

2.1

3.6

1.9

2.4

2.8

3.5

2.5

3.1

3.3

4.1

so Note 1: PCI clock at 33MHz

Ob Table 4-7. 3.3V Power Consumptions (VDD)

) - HCLK

t(s (MHz)

CPUCLK

(MHz)

MCLK

(MHz)

c 66

133 (x2)

66

rodu 66

133 (x2)

90

DCLK

(MHz)

6.26

135

6.26

135

PMU

(State)

Full Speed

Full Speed

PMax

(mW)

130

215

150

240

te P Table 4-8. PLL Power Consumptions

sole VDD_DCLK_PLL

bVDD_DEVCLK_PLL

OVDD_HCLKI_PLL

PLL name

PMax (mW)

VDD_PLL = 2.45V

VDD_PLL = 2.7V

5

10

5

10

5

10

VDD_HCLKO_PLL

5

10

VDD_MCLKI_PLL

5

10

VDD_MCLKO_PLL

5

10

VDD_PCICLK_PLL

5

10

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