STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

4.5.1. POWER ON SEQUENCE

Figure 4-2. CLK Timing Measurement Points

T1

T2

VIH (MIN)

VRef

CLK VIL (MAX)

T5

T3

T4

t(s) LEGEND:

T1 - One Clock Cycle

T2 - Minimum Time at VIH

T3 - Minimum Time at VIL

T4 - Clock Fall Time

T5 - Clock Rise Time

c NOTE; All sIgnals are sampled on the rising edge of the CLK.

rodu Figure 4-3 describes the power-on sequence of

P the STPC, also called cold reset.

te There is no dependency between the different

le power supplies and there is no constraint on their

rising time.

bso SYSRSTI# as no constraint on its rising edge but

must stay active until power supplies are all within

O specifications, a margin of 10µs is even

- recommended to let the STPC PLLs and strap

Obsolete Product(s) options stabilize.

Strap Options are continuously sampled during

SYSRSTI# low and must remain stable. Once

SYSRSTI# is high, they MUST NOT CHANGE

until SYSRSTO# goes high.

Bus activity starts only few clock cycles after the

release of SYSRSTO#. The toggling signals

depend on the STPC configuration.

In ISA mode, activity is visible on PCI prior to the

ISA bus as the controller is part of the south

bridge.

In Local Bus mode, the PCI bus is not accessed

and the Flash Chip Select is the control signal to

monitor.

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