STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

4.5.2 RESET SEQUENCE

Figure 4-4 describes the reset sequence of the

STPC, also called warm reset.

The constraints on the strap options and the bus

activities are the same as for the cold reset.

The SYSRSTI# pulse duration must be long

enough to have all the strap options stabilized and

must be adjusted depending on resistor values.

Figure 4-4. Reset timing diagram

It is mandatory to have a clean reset pulse without

glitches as the STPC could then sample invalid

strap option setting and enter into an umpredicta-

ble mode.

While SYSRSTI# is active, the PCI clock PLL runs

in open loop mode at a speed of few 100’s KHz.

14 MHz

SYSRSTI#

t(s) ISACLK

duc Strap Options MD[63:0]

Pro HCLK

olete PCI_CLK

Obsolete Product(s) - Obs SYSRSTO#

1.6 V

VALID CONFIGURATION

2.3 ms

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