STPCI2 查看數據表（PDF） - STMicroelectronics
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STPCI2 Datasheet PDF : 108 Pages
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STPC® ATLAS
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10, Table 4-11 lists the AC
characteristics of the SDRAM interface. The
Figure 4-5. SDRAM Timing Diagram
MCLKx clocks are the input clock of the SDRAM
devices.
MCLKx
Tdelay
MCLKI
Thigh
Tcycle
Tlow
) STPC.output
te Product(s STPC.input
Thold
Toutput (max)
Toutput (min)
Tsetup
Obsole Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
) - Name
t(s Tcycle
Thigh
uc Tlow
Prod Tdelay
Obsolete Toutput
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to RAS# Valid
MCLKI to CAS# Valid
MCLKI to CS# Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MCLKI to MA[ ] Outputs Valid
Min Typ Max Unit
11
ns
4
ns
4
ns
1
ns
1
ns
0.5
1
1.5
ns
1.6
5.2
ns
1.6
5.2
ns
1.6
5.2
ns
1.35
5.2
ns
1.35
5.2
ns
1.6
5.2
ns
MCLKI to MWE# Valid
1.6
5.2
ns
Tsetup MD[63:0] setup to MCKLI
4.7
ns
Thold MD[63:0] hold from MCKLI
-0.36
2.3
ns
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK activated and set to 0
The PC100 memory is recommended to reach 90MHz operation.
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