STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

Table 4-14. ISA Bus AC Timing

Name Parameter

Min

Max

Units

38

ALE# asserted to read data valid

38b Memory access to 16-bit ISA Slave Standard Cycle

4T

Cycles

38e Memory access to 8-bit ISA Slave Standard Cycle

10T

Cycles

38h I/O access to 16-bit ISA Slave Standard Cycle

4T

Cycles

38l I/O access to 8-bit ISA Slave Standard Cycle

10T

Cycles

41

SA[19:0] SBHE valid to IOCHRDY negated

41a Memory access to 16-bit ISA Slave

6T

Cycles

41b Memory access to 8-bit ISA Slave

12T

Cycles

41c I/O access to 16-bit ISA Slave

6T

Cycles

41d I/O access to 8-bit ISA Slave

12T

Cycles

42

SA[19:0] SBHE valid to read data valid

42b Memory access to 16-bit ISA Slave Standard cycle

4T

Cycles

42e Memory access to 8-bit ISA Slave Standard cycle

10T

42h I/O access to 16-bit ISA Slave Standard cycle

4T

) 42l I/O access to 8-bit ISA Slave Standard cycle

10T

t(s 47

MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated

c 47a Memory access to 16-bit ISA Slave

2T

u 47b Memory access to 8-bit ISA Slave

5T

rod 47c I/O access to 16-bit ISA Slave

2T

47d I/O access to 8-bit ISA Slave

5T

P 48

MEMR#, SMEMR#, IOR# asserted to read data valid

te 48b Memory access to 16-bit ISA Slave Standard Cycle

2T

le 48e Memory access to 8-bit ISA Slave Standard Cycle

5T

o 48h I/O access to 16-bit ISA Slave Standard Cycle

2T

s 48l I/O access to 8-bit ISA Slave Standard Cycle

5T

b 54

IOCHRDY asserted to read data valid

O 54a Memory access to 16-bit ISA Slave

1T(R)/2T(W)

) - 54b Memory access to 8-bit ISA Slave

1T(R)/2T(W)

t(s 54c I/O access to 16-bit ISA Slave

1T(R)/2T(W)

54d I/O access to 8-bit ISA Slave

1T(R)/2T(W)

duc 55a

IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#,

IOR#, IOW# negated

1T

ro 55b

IOCHRY asserted to MEMR#, SMEMR# negated (refresh)

1T

56

IOCHRDY asserted to next ALE# asserted

2T

P 57

IOCHRDY asserted to SA[19:0], SBHE invalid

2T

te 58

MEMR#, IOR#, SMEMR# negated to read data invalid

0T

le 59

MEMR#, IOR#, SMEMR# negated to data bus float

0T

o61

Write data before MEMW# asserted

bs 61a Memory access to 16-bit ISA Slave

2T

O 61b

Memory access to 8-bit ISA Slave (Byte copy at end of

start)

2T

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

61

Write data before SMEMW# asserted

61c Memory access to 16-bit ISA Slave

2T

Cycles

61d Memory access to 8-bit ISA Slave

2T

Cycles

61

Write Data valid before IOW# asserted

Note: The signal numbering refers to Figure 4-8

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