STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

Table 4-14. ISA Bus AC Timing

Name Parameter

Min

Max

Units

24i Memory access to 16-bit ISA Slave - 4BCLK

10T

Cycles

24k Memory access to 8-bit ISA Slave - 3BCLK

10T

Cycles

24l Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

24

IOR#, IOW# asserted before SA[19:0]

24o I/O access to 16-bit ISA Slave Standard cycle

19T

Cycles

24r I/O access to 16-bit ISA Slave Standard cycle

19T

Cycles

25

MEMR#, MEMW# asserted before next ALE# asserted

25b Memory access to 16-bit ISA Slave Standard cycle

10T

Cycles

25d Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

25

SMEMR#, SMEMW# asserted before next ALE# asserted

25e Memory access to 16-bit ISA Slave - 2BCLK

10T

Cycles

25f Memory access to 16-bit ISA Slave Standard cycle

10T

Cycles

25h Memory access to 8-bit ISA Slave Standard cycle

10T

25

IOR#, IOW# asserted before next ALE# asserted

) 25i I/O access to 16-bit ISA Slave Standard cycle

10T

t(s 25k I/O access to 16-bit ISA Slave Standard cycle

10T

c 26

MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted

u 26b Memory access to 16-bit ISA Slave Standard cycle

12T

rod 26d Memory access to 8-bit ISA Slave Standard cycle

12T

26

SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted

P 26f Memory access to 16-bit ISA Slave Standard cycle

12T

te 26h Memory access to 8-bit ISA Slave Standard cycle

12T

le 26

IOR#, IOW# asserted before next IOR#, IOW# asserted

o 26i I/O access to 16-bit ISA Slave Standard cycle

12T

s 26k I/O access to 8-bit ISA Slave Standard cycle

12T

b 28

Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted

O 28a Memory access to 16-bit ISA Slave

3T

) - 28b Memory access to 8-bit ISA Slave

3T

t(s 28

Any command negated to IOR#, IOW# asserted

28c I/O access to ISA Slave

3T

uc 29a

MEMR#, MEMW# negated before next ALE# asserted

1T

d 29b

SMEMR#, SMEMW# negated before next ALE# asserted

1T

ro 29c

IOR#, IOW# negated before next ALE# asserted

1T

P 33

LA[23:17] valid to IOCHRDY negated

33a Memory access to 16-bit ISA Slave - 4 BCLK

8T

te33b Memory access to 8-bit ISA Slave - 7 BCLK

14T

le 34

LA[23:17] valid to read data valid

so 34b Memory access to 16-bit ISA Slave Standard cycle

8T

b 34e Memory access to 8-bit ISA Slave Standard cycle

14T

O 37

ALE# asserted to IOCHRDY# negated

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

37a Memory access to 16-bit ISA Slave - 4 BCLK

6T

Cycles

37b Memory access to 8-bit ISA Slave - 7 BCLK

12T

Cycles

37c I/O access to 16-bit ISA Slave - 4 BCLK

6T

Cycles

37d I/O access to 8-bit ISA Slave - 7 BCLK

12T

Cycles

Note: The signal numbering refers to Figure 4-8

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