CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
The register allocation is shown in Table 16-1. An ‘x’ denotes the actual data field, and any unused bit
should be programmed with a logic zero.
NOTE: Do not access any register at any location other than that shown as the actual register map is multiple-
mapped.
Table 16-1. The Video and Sound Macrocell Register Allocation
Address
(Hex)
Register Name
0xxxxxxx
100000xx
20000000
300000xx
310000xx
4xxxxxxx
5xxxxxxx
6xxxxxxx
7xxxxxxx
8000xxxx
8100xxxx
8200xxxx
8300xxxx
8400xxxx
8500xxxx
8600xxxx
8700xxxx
8800xxxx
Video Palette
Video Palette Address
Reserved
LCD Offset 0
LCD Offset 1
Border Color
Cursor Palette Logical Color 1
Cursor Palette Logical Color 2
Cursor Palette Logical Color 3
Horizontal Cycle
Horizontal Sync Width
Horizontal Border Start
Horizontal Display Start
Horizontal Display End
Horizontal Border End
Horizontal Cursor Start
Reserved
Test
Page
142
142
143
143
144
144
144
144
145
145
145
146
146
146
147
147
147
Address
(Hex)
Register Name
8C00xxxx
9000xxxx
9100xxxx
9200xxxx
9300xxxx
9400xxxx
9500xxxx
9600xxxx
9700xxxx
9800xxxx
9A00xxxx
9C00xxxx
B00000x
B10000x
C00xxxxx
D000xxxx
E00xxxxx
F000xxxx
Test
Vertical Cycle
Vertical Sync Width
Vertical Border Start
Vertical Display Start
Vertical Display End
Vertical Border End
Vertical Cursor Start
Vertical Cursor End
Test
Test
Test
Sound Frequency
Sound Control
External
Frequency Synthesis
Control
Data Control
Page
147
147
148
148
148
149
149
149
150
150
150
150
154
155
151
152
153
154
The External, Control, Sound Control, and Data Control registers all contain bits that are not initialized at
power up. These registers must be programmed before the video and sound macrocell can operate prop-
erly.
June 1997
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
141
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