CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

16.7 Horizontal Cycle Register (HCR): Address 0x80

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1000 0000

XXXXXXXXXXX 00

HCR value

This register defines the period, in pixels, of the horizontal scan that is, display time + retrace time. This

is a 14-bit register of which the bottom 2 bits must be programmed to ‘0’. If N pixels are required in the

horizontal scan period, then value (N − 8) should be programmed into the HCR (N must be a multiple of 4).

16.8 Horizontal Sync Width Register (HSWR): Address 0x81

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 0 0 0001

XXXXXXXXXXXX0

HSWR value

This register defines the period, in pixels, of the HSYNC pulse. This is a 14-bit register of which the bottom

bit must be programmed to ‘0’. If N pixels are required in the HSYNC pulse, then value (N − 8) should be

programmed into the HSWR (N must be a multiple of 2).

16.9 Horizontal Border Start Register (HBSR): Address 0x82

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 000 0010

XXXXXXXXXXXX 0

HBSR value

This register defines the time, in pixels, from the start of the HSYNC pulse to the start of the border display.

This is a 14-bit register of which the bottom bit must be programmed to ‘0’. If N pixels are required in this

time, then program the value (N − 12) into the HBSR (N must be a multiple of 2).

NOTE: This register must always be programmed, even when a border is not required. If a border is not required,

then the value in the HBSR must be set to start the border in the same place as the display starts (that is,

NHBSR = NHDSR).

June 1997

ADVANCE DATA BOOK v2.0

THE VIDEO SOUND AND PROGRAMMER’S MODEL

145

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