CL-PS7500FE 查看數據表（PDF） - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.17 Vertical Sync Width Register (VSWR): Address 0x91
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1001 0001
XXXXXXXXXXXXX
VSWR value
This 13-bit register defines the width, in units of a raster, of the VSYNC pulse. If N rasters are required in
the VSYNC pulse, then program the value (N − 2) into the VSWR. The minimum value allowed for N is 2.
16.18 Vertical Border Start Register (VBSR): Address 0x92
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1001 0010
XXXXXXXXXXXXX
VBSR value
This 13-bit register defines the time, in units of a raster, from the start of the VSYNC pulse to the start of
the border display. If N rasters are required in this time, then program the value (N − 1) into the VBSR. If
no border is required, this register must still be programmed, in this case to the same value as the VDSR.
16.19 Vertical Display Start Register (VDSR): Address 0x93
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1001 0011
XXXXXXXXXXXXX
VDSR value
This 13-bit register defines the time, in units of a raster, from the start of the VSYNC pulse to the start of
the video display. If N rasters are required in this time, then program the value (N − 1) into the VDSR.
148
THE VIDEO SOUND AND PROGRAMMER’S MODEL
ADVANCE DATA BOOK v2.0
June 1997
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