FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

PF is set to a "1" independent of the state of

the PIE bit. PF being a "1" sets the IRQF bit

and initiates an IRQB signal when PIE is also a

"1". The PF bit is cleared by RESET_DRV or by

a read of Register C .

AF

UF

The update-ended interrupt flag bit is set after

each update cycle. When the UIE bit is also a

"1", the "1" in UF causes the IRQF bit to be set

and asserts IRQB. A RESET_DRV or a read of

Register C causes UF to be cleared.

The alarm interrupt flag when set to a "1"

indicates that the current time has matched the

alarm time. A "1" in AF causes a "1" to appear in

IRQF and the IRQB port to go low when the AIE

bit is also a "1". A RESET_DRV or a read of

Register C clears the AF bit.

b3-0

The unused bits of Register C are read as zeros

and cannot be written.

REGISTER D (DH) - BITS[7,6] ARE READ-ONLY, BITS[5:0] ARE READ/WRITE

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

VRT

0

Date Alarm

VRT

b5:b0

When a "1", this bit indicates that the contents

of the RTC are valid. A "0" appears in the VRT

bit when the battery voltage is low. The VRT bit

is a read-only bit, which can only be set by a

read of Register D.

Refer to Power

Management for the conditions when this bit is

reset. The processor program can set the VRT

bit when the time and calendar are initialized to

indicate that the time is valid.

b6

Read as zero and cannot be written.

Date Alarm; These bits store the date of month

alarm value. If set to 000000b, then a don’t

care state is assumed. The host must configure

the date alarm for these bits to do anything, yet

they can be written at any time. If the date

alarm is not enabled, these bits will return zeros.

These bits are not affected by RESET_DRV.

Note: Bits[6:0] are not accessible during an

update cycle.

REGISTER 7E (7Eh) CONTROL REGISTER 1

Default is 0; cleared upon Vbat POR. This

register is battery backed-up.

D7

D6

D5

D4

XTAL_

0

0

0

CAP

D3

D2

D1

D0

0

VTR_POR VTR_POR AL_REM_

_EN

_OFF

EN

145

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