FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

FIGURE 3 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM

Button

L

OFF_EN

OFF_DLY

Button Input

ED; PG

SP1

ED; L

EN1

nSPOFF1

SPx

ED; L

ENx

nSPOFF1

Delay2

nSPOFF

Logic

VTR_POR_EN

VTR POR

AL_REM_EN

Alarm

nSPOFF1

Logic

VTR

Delay1

Flip

Flop 1

D

Q

CLR

VTR_POR_OFF

VTR POR

VBAT POR

Soft Power

Logic

Off nSPOFF1

VTR POR With

Vbat<1.2V

nBINT

OFF_DLY

nPowerOn

Open Collector

Type Output

PWRBTNOR_EN

Override

Timer

PWRBTNOR_STS

A transition on the Button input, or on any enabled SPx inputs causes the nPowerOn output to go active low.

A low pulse on the Soft Power Off signal, a Vbat POR, a VTR POR with Vbat<1.2V, or Power Button Override Event causes

nPowerOn to float.

ED;PG = Edge Detect, Pulse Generator

ED;L = Edge Detect and Latch

Note 1: All soft power management functions run off of VTR. When VTR is present, it supplies power

to the RTC. When VTR is not present, Vbat supplies power to the RTC and Flip Flop 1.

Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine.

Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 in

the soft power management circuit to come up ‘on’ if an alarm occurred when VTR was not

present. This is gated into wakeup circuitry. Refer to the AL_REM_EN Bit description in the

RTC Control Register section for more information.

Note 4: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 to

come up ‘off’ after a VTR POR, see VTR_POR_OFF.

149

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