FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

The IRQF bit in Register C is a "1" whenever the

IRQB port is being driven low.

Frequency Divider

The RTC has 22 binary divider stages following

the clock input. The output of the divider is a 1

Hz signal to the update-cycle

logic. The divider is controlled by the three

divider bits (DV3-DV0) in Register A. As shown

in Table 66 the divider control bits can select the

operating mode, or be used to hold the divider

chain reset which allows precision setting of the

time. When the divider chain is changed from

reset to the operating mode, the first update

cycle is one-half second later. The divider

control bits are also used to facilitate testing of

the RTC.

Periodic Interrupt Selection

The periodic interrupt allows the IRQB port to be

triggered from once every 500 ms to once every

122.07 µs. As Table 67 shows, the periodic

interrupt is selected with the RS0-RS3 bits in

Register A. The periodic interrupt is enabled

with the PIE bit in Register B.

147

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