C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 14.1. OSCICL: Internal Oscillator Calibration

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x8B

SFR Page: F

Bits 7-0: OSCICL: Internal Oscillator Calibration Register

This register calibrates the internal oscillator period. The reset value for OSCICL defines the

internal oscillator base frequency. The reset value is factory calibrated to generate an inter-

nal oscillator frequency of 24.5 MHz.

SFR Definition 14.2. OSCICN: Internal Oscillator Control

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

Reset Value

IOSCEN IFRDY

-

-

-

-

IFCN1 IFCN0 11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x8A

SFR Page: F

Bit7:

Bit6:

Bits5-2:

Bits1-0:

IOSCEN: Internal Oscillator Enable Bit.

0: Internal Oscillator Disabled

1: Internal Oscillator Enabled

IFRDY: Internal Oscillator Frequency Ready Flag.

0: Internal Oscillator is not running at programmed frequency.

1: Internal Oscillator is running at programmed frequency.

Reserved.

IFCN1-0: Internal Oscillator Frequency Control Bits.

00: SYSCLK derived from Internal Oscillator divided by 8.

01: SYSCLK derived from Internal Oscillator divided by 4.

10: SYSCLK derived from Internal Oscillator divided by 2.

11: SYSCLK derived from Internal Oscillator divided by 1.

174

Rev. 1.5

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