C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 14.1. Internal Oscillator Electrical Characteristics

–40 to +85 °C unless otherwise specified.

Parameter

Conditions

Min Typ Max

Calibrated Internal Oscillator 

Frequency

24 24.5 25

Internal Oscillator Supply Current OSCICN.7 = 1

(from VDD)

External Clock Frequency

TXCH (External Clock High Time)

TXCL (External Clock Low Time)

— 450 —

0

— 30

15

—

—

15

—

—

Units

MHz

µA

MHz

ns

ns

14.2. External Oscillator Drive Circuit

The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A

CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/

resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. In RC,

capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 and/or XTAL1

pin(s) as shown in Option 2, 3, or 4 of Figure 14.1. The type of external oscillator must be selected in the

OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Defini-

tion 14.4).

14.3. System Clock Selection

The CLKSL bit in register CLKSEL selects which oscillator is used as the system clock. CLKSL must be

set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator may still

clock peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system

clock may be switched on-the-fly between the internal and external oscillator, so long as the selected oscil-

lator is enabled and has settled. The internal oscillator requires little start-up time and may be enabled and

selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typi-

cally require a start-up time before they are settled and ready for use as the system clock. The Crystal

Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To

avoid reading a false XTLVLD in crystal mode, software should delay at least 1 ms between enabling the

external oscillator and checking XTLVLD. RC and C modes typically require no startup time.

SFR Definition 14.3. CLKSEL: Oscillator Clock Selection

R

R

R

R

R

R

R

R/W

Reset Value

-

-

-

-

-

-

-

CLKSL 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x97

SFR Page: F

Bits7-1:

Bit0:

Reserved.

CLKSL: System Clock Source Select Bit.

0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in OSCICN.

1: SYSCLK derived from the External Oscillator circuit.

Rev. 1.5

175

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